1. Field of the Invention
The present invention relates to a logic circuit verification device for a semiconductor integrated circuit for verifying a logic circuit of a semiconductor integrated circuit such as an LSI (Large Scale Integrated) circuit, which is described on a computer by using hardware description language (hereinafter referred to as "HDL"), in conformity with a cycle based simulation method, a static timing verification method, a logic circuit simulation method based on an event-driven system or the like.
2. Description of the Prior Art
According to a conventional logic circuit verification device for a semiconductor integrated circuit, a logic circuit is verified by using a cycle based simulation/static timing verification method based on cycle based simulation or static timing verification, or the logic circuit simulation method based on the event-driven system.
According to the cycle based simulation/static timing verification method, the verification of a logic circuit is done by checking the operation of sending and receiving signals among circuit elements constituting a semiconductor integrated circuit, for example flip-flop circuits, on the occurrence of changing of an event of a clock that constitutes a trigger for causing state change; and then by analyzing delay time and operational timing of a memory element, such as a register (a flip-flop circuit or a latch circuit), a combinational circuit or the like.
Further, according to the logic circuit simulation based on the event-driven system, the verification of a logic circuit is done by reproducing a total operation of an actual circuit after inputting delay time, operational timing and functions of a register, a combination circuit or the like into the logic circuit verification device.
Although high speed verification of a logic circuit can be achieved in the cycle based simulation/static timing verification method compared with the logic circuit simulation based on the event-driven system, the verification of a logic circuit can be carried out only in respect of a synchronous circuit block including a combinational circuit portion where a signal is transmitted in 1 cycle or less of a clock pulse in the combinational circuit portion connected between registers (hereinafter, referred to as "single cycle path"). In respect of a synchronous circuit block including a combinational circuit portion where 2 cycles or more of clock pulses are needed in transmitting a signal between registers interposing the combinational circuit (hereinafter, referred to as "multiple cycle path"), the verification had to be carried out by using the logic circuit simulation based on the event-driven system.
The conventional logic circuit verification device for a semiconductor integrated circuit is constituted as described above. This, when there are many asynchronous circuit portions or synchronous circuit blocks of multiple cycle path in a logic circuit, limited a range of synchronous circuits to which the cycle based simulation/static timing verification method, a high-speed logic verification tool, is applicable, and resulted in a problem of prolonging a time for logic verification.